clash-lib: CAES Language for Synchronous Hardware - As a Library

[ bsd2, hardware, library ] [ Propose Tags ]

Clash is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The Clash compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of Clash:

This package provides:

Front-ends (for: parsing, typecheck, etc.) are provided by separate packages:

Prelude library: http://hackage.haskell.org/package/clash-prelude


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Versions [faq] 0.2, 0.2.0.1, 0.2.1, 0.2.2, 0.2.2.1, 0.3, 0.3.0.1, 0.3.0.2, 0.3.0.3, 0.3.0.4, 0.3.1, 0.3.2, 0.4, 0.4.1, 0.5, 0.5.1, 0.5.2, 0.5.3, 0.5.4, 0.5.5, 0.5.6, 0.5.7, 0.5.8, 0.5.9, 0.5.10, 0.5.11, 0.5.12, 0.5.13, 0.6, 0.6.1, 0.6.2, 0.6.3, 0.6.4, 0.6.5, 0.6.6, 0.6.7, 0.6.8, 0.6.9, 0.6.10, 0.6.11, 0.6.12, 0.6.13, 0.6.14, 0.6.15, 0.6.16, 0.6.17, 0.6.18, 0.6.19, 0.6.20, 0.6.21, 0.7, 0.7.1, 0.99, 0.99.1, 0.99.2, 0.99.3, 1.0.0, 1.0.1, 1.2.0 (info)
Change log CHANGELOG.md
Dependencies aeson (>=0.6.2.0 && <1.5), ansi-terminal (>=0.8.0.0 && <0.11), attoparsec (>=0.10.4.0 && <0.14), base (>=4.10 && <5), binary (>=0.8.5 && <0.11), bytestring (>=0.10.0.2 && <0.11), clash-prelude (==1.0.*), concurrent-supply (>=0.1.7 && <0.2), containers (>=0.5.0.0 && <0.7), data-binary-ieee754 (>=0.4.4 && <0.6), deepseq (>=1.3.0.2 && <1.5), directory (>=1.2.0.1 && <1.4), errors (>=1.4.2 && <2.4), exceptions (>=0.8.3 && <0.11.0), filepath (>=1.3.0.1 && <1.5), ghc (>=8.2.0 && <8.9), hashable (>=1.2.1.0 && <1.4), hint (>=0.7 && <0.10), integer-gmp (==1.0.*), interpolate (>=0.2.0 && <1.0), lens (>=3.9.2 && <4.19), mtl (>=2.1.2 && <2.3), parsers (>=0.12.8 && <1.0), prettyprinter (>=1.2.0.1 && <2.0), primitive (>=0.5.0.1 && <1.0), process (>=1.1.0.2 && <1.7), reducers (>=3.12.2 && <4.0), template-haskell (>=2.8.0.0 && <2.16), temporary (>=1.2.1 && <1.4), text (>=1.2.2 && <1.3), text-show (>=3.7 && <3.9), time (>=1.4.0.1 && <1.10), transformers (>=0.5.2.0 && <0.6), trifecta (>=1.7.1.1 && <2.2), unordered-containers (>=0.2.3.3 && <0.3), vector (>=0.11 && <1.0), vector-binary-instances (>=0.2.3.5 && <0.3) [details]
License BSD-2-Clause
Copyright Copyright © 2012-2016, University of Twente, 2016-2019, Myrtle Software Ltd, 2017-2019, QBayLogic B.V., Google Inc.
Author The Clash Authors
Maintainer QBayLogic B.V. <devops@qbaylogic.com>
Revised Revision 1 made by QBayLogic at Wed Mar 4 16:50:33 UTC 2020
Category Hardware
Home page http://www.clash-lang.org/
Bug tracker http://github.com/clash-lang/clash-compiler/issues
Source repo head: git clone https://github.com/clash-lang/clash-compiler.git
Uploaded by QBayLogic at Thu Oct 17 10:19:16 UTC 2019
Distributions NixOS:1.2.0
Downloads 35064 total (2641 in the last 30 days)
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Modules

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Flags

NameDescriptionDefaultType
debug

Build a debug compiler

DisabledManual
history

Emit rewrite history to disk

DisabledManual
unittests

You can disable testing with unittests using -f-unittests.

EnabledManual

Use -f <flag> to enable a flag, or -f -<flag> to disable that flag. More info

Downloads

Note: This package has metadata revisions in the cabal description newer than included in the tarball. To unpack the package including the revisions, use 'cabal get'.

Maintainer's Corner

For package maintainers and hackage trustees


Readme for clash-lib-1.0.1

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clash-lib - Clash compiler, as a library

  • See the LICENSE file for license and copyright details

Clash - A functional hardware description language

Clash is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. The Clash compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of Clash:

  • Strongly typed (like VHDL), yet with a very high degree of type inference, enabling both safe and fast prototying using consise descriptions (like Verilog).

  • Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.

  • Higher-order functions, with type inference, result in designs that are fully parametric by default.

  • Synchronous sequential circuit design based on streams of values, called Signals, lead to natural descriptions of feedback loops.

  • Support for multiple clock domains, with type safe clock domain crossing.

Support

For updates and questions join the mailing list clash-language+subscribe@googlegroups.com or read the forum